Grant Proposal for Programmable Decoder for Supporting Almost Any ISA

General
1

As suggested a while ago by Michiel, we should submit our next grant proposal to NLnet so it can be ready to work on when we finish our current grant. We should submit it before the Dec 1st deadline.

I think we should have the grant be for working on the idea I came up with for having a programmable decoder that's kinda a pipelined FPGA that decodes the most common instructions into μOps and stores them in a μOp cache, instructions that can't be handled that way trap for emulation. For programming the decoder I want to build a special compiler that compiles qemu (or similar) into a combination emulator and bitstream for the decoder. The compiler works by basically using Clang to compile Qemu to LLVM IR and then we have it process the LLVM IR of Qemu's instruction decoder/jit-translation function to extract the possible instructions, their encodings, and the operations they translate to (conveniently qemu calls a bunch of TCG functions for encoding the operations, so we can mostly just see which TCG functions are called). the compiler then tries to convert those operations to a set of μOps and if it succeeds then it tries to add it to the programmable decoder's bitstream. The emulation trap will just run Qemu's code compiled to PowerISA.

That process should allow us to support running older 32/64-bit x86 (since the patents expired), RISC-V, and the full set of PowerISA instructions (allowing the dedicated PowerISA decoder to only support the simpler instructions and instructions needed for running emulation traps rather than having to support the whole ISA).
We can also support basically any other ISA supported by Qemu, but we'd need to avoid violating patents on other ISAs, one possible way around that is that since running Qemu on any computer doesn't have patent issues, we could argue that our design is just a computer optimised for running Qemu faster since none of the hardware is specifically for any patented ISA like modern x86 or AArch64, other than in unpatentable ways (e.g. supporting x86's EFLAGS register since any possible patents have expired, or maybe supporting Armv7's flags since e.g. I don't expect having an overflow flag is patentable).

We can also include further improvements to the CPU in the grant, e.g. adding FP ops and paging. Since this is not our first grant we may be able to ask for more than €50000 based on presumably having completed our current grant by the time NLnet approves our proposal.

I'm planning on writing up a proposal soon and then posting it for review, who all is interested in helping out with the grant? I can add you to the grant proposal.

2

Definitively a good proposal. Qemu is slow but it can translate almost any ISA to a different kind of ISA. Other projects that I find interesting are Box86 that compiles x86 to RISC arcitectures and the Dolphin Emulator which has a jit backend for x86 and ARM.

3

One of the other reasons I picked Qemu over other emulators is that Intel and other CPU manufacturers contribute to Qemu, so the GPLv2's patent license clause might cover running Qemu on our CPU with the programmable decoder.

4

From past discussions it seems there really is some people interested in a multi-ISA CPU.

I’ll help as far as I can, you can add me to the proposal.

Would doing a Linux port of the CPU on a SoC running on an FPGA be appropriate for this grant already? I suppose it would involve some QEMU emulation at first.

5

That depends on how big the grant can be, if it's €50000, there's no way that'll fit.

I'm kinda thinking qemu for handling emulation traps will be running on bare hardware (so like risc-v's m-mode, but powerpc) and then unmodified powerpc/x86/risc-v/etc. linux can run on top of that, though we will want to add support for switching which architecture is used for running stuff in kvm inside linux and/or add support for qemu acting like a hypervisor like xen does but with choice of architecture for each vm.

6

not that that part has to happen as part of this grant, just that it sounds likely to be useful in the future.