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Welcome to Libre-Chip Forum! :wave:
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0
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25
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July 8, 2024
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About the General category
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7
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July 8, 2024
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Draft NLNet Grant Proposal -- Libre-Chip's CPU with a Programmable Decoder to Run Multiple ISAs at Full Speed
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10
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November 28, 2025
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Grant Proposal for Programmable Decoder for Supporting Almost Any ISA
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5
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29
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October 27, 2025
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Open Source Chip Design Workshop
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1
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21
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October 18, 2025
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Schematics: Libre Chip Execution Unit — Discussion & Suggestions
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10
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41
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September 5, 2025
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Idea for changing the register file and muxing to make it faster
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29
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56
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August 30, 2025
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Ideas for what to do initially
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2
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73
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August 26, 2025
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Idea for maybe allowing much wider fetch/rename/etc. widths in a CPU
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13
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129
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August 24, 2025
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Another HDL in Rust
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3
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57
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August 24, 2025
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Congratulations — and an ISA proposal
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5
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15
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August 22, 2025
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Draft of NLnet Grant Announcement
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6
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30
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August 19, 2025
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coming up with a more specific grant budget
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8
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28
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July 22, 2025
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starting working on a nlnet grant proposal
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4
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39
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December 1, 2024
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I wrote a mostly-working instruction extractor for the OPF PowerISA 3.1C pdf
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0
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25
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October 28, 2024
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libre-chip/cpu CI issues
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2
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53
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October 22, 2024
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Released fayalite v0.2.0
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0
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31
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October 18, 2024
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Proposal for Libre-Chip's First CPU Architecture
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6
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79
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October 13, 2024
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Is Fayalite ready for releasing version 0.2.0?
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1
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30
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October 13, 2024
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Testing creating a new thread via email
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0
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27
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October 7, 2024
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Create Discourse topic by email
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1
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22
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October 7, 2024
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Formal verification in Fayalite
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3
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39
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October 7, 2024
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Syntax suggestions for Fayalite
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3
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40
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October 7, 2024
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Simulator for Fayalite
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1
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52
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September 8, 2024
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Adding Docs for Fayalite
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3
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46
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July 24, 2024
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