As discussed in the last meeting, we should figure out what we want to do initially:
It was suggested to try to make a minimal PowerISA softcore for a FPGA that we can run a blinky LED program on as a demo.
I suggested we work on making an OoO Superscalar core -- to make it more minimal we can just reduce the resources to the absolute minimum needed to run (e.g. have just branch, ALU, and load/store units, have fetch/decode width be 1 instruction, skip caches for now), though we should definitely plan ahead and add stuff that will be needed later, such as the ability for loads/stores to trap.
I have an idea for a distributed register file that allows us to only need dual port sram for the registers (allowing it to be more efficient on a FPGA. maybe on ASIC too?), basically every unit that writes registers logically has its own set of registers that it is the only thing that writes to them, and then every unit that needs to read registers has an instance of every unit's output registers sram. if the unit's register sets are too small and can't hold enough for all ISA-level registers, then we'd have a separate unit that is only the ISA-level registers, and the register renamer will insert moves when necessary.