I was thinking of feeding the output to iverilog or similar, but if we need some more complex interaction then yosys cxxrtl or verilator or something else could work well. I wasn't thinking it's as good an idea to have simulation directly done by fayalite since that would be somewhat complex and could possibly give different results than simulating verilog due to bugs that fayalite might have. that said, now that I'm thinking about it more, it might serve as a way to find bugs in fayalite's firrtl backend if simulation doesn't match verilog simulation.