Simulator for Fayalite

Hi Jacob,

What are your thoughts about simulation in Fayalite? Are you thinking about Rust testbenches?

How about a native Rust event driven simulator? Or feed the Fayalite Verilog output to Verilator? Maybe add Rust bindings to it?

I was looking at Arcilator. This does seems to output something:

firtool example_module.fir --ir-hw -o example_module.hdl
arcilator --emit-llvm example_module.hdl

Maybe one could generate a Rust binding to the above LLVM object code?

Regards,

Cesar

I was thinking of feeding the output to iverilog or similar, but if we need some more complex interaction then yosys cxxrtl or verilator or something else could work well. I wasn't thinking it's as good an idea to have simulation directly done by fayalite since that would be somewhat complex and could possibly give different results than simulating verilog due to bugs that fayalite might have. that said, now that I'm thinking about it more, it might serve as a way to find bugs in fayalite's firrtl backend if simulation doesn't match verilog simulation.