Well, that makes sense because your design is simpler.
I think it is a good idea to start simple.
If you ever want to use my high-performance execution unit which allows for 20% higher clock rate, below are the schematics I made so far, and some of my notes.
- provided a new schematic for the execution unit, v5.0
- provided an example schematic for L2RF ALU (but timings are very tight)
(Simple ALU unit roughly sketched, as an example)
- 7 units total (including L2RF unit)
- proposal for 5 unit types: A, S, M, D, L2RF
- The Unit type D can now produce two 64-bit results per clock cycle
- it shares one output register with the L2RF unit
- Tried to assign operations to each unit type (in text below)
- The FO4 gate delays are rough guestimates
- I need data on gate delays to be able to draw and synchronize the ALUs
- How may gate delays for:
- 1 level multiplexer ( 2-to-1) (assumed 2.3 gd)
- 2 level multiplexer ( 4-to-1) (assumed 4.6 gd)
- 3 level multiplexer ( 8-to-1) (assumed 6.9 gd)
- 4 level multiplexer (16-to-1) (assumed 9.2 gd)
- from D-latch open to output valid (i.e. latency of registers) (assumed 2 gd)
- from output register latch open to fast mux (assumed 9 gd)
- for each arithmetic / logic operation
FO4 gate delays:
One Clock Cycle:
9 gate delays from output register latch open, to FAST MUX
+ 7 gate delays: fast mux (8 to 1)
= 16 gate delays from output register latch open, to BIG ALU
+ 11 gate delays: combinatorial logic for add/sub/cmp or shift/rot
= 27 gate delays TOTAL (FO4)
11 gate delays from output register latch open, to INPUT MUX
22 gate delays from output register latch open, to INPUT REGS
Intra-cycle latches timing:
- input regs open latches at 0 gate delays (intra-cycle timing)
- L2regs open latches at 2 gate delays (intra-cycle timing)
- output regs open latches at 5 gate delays (intra-cycle timing)
Unit 1 (Type S): << Should be the tightest unit regarding max. clock speed
shift/rot ( 1 cycle )
Units 2, 3 (Type A): << Should also be the tightest unit regarding max. clock speed
add/sub/cmp ( 1 cycle )
Units 4, 5 (Type M): << Should not be very tight; if it is, then it should be trimmed
mul pipelined ( 4 cycles) line 0 ----=> muxed into line 2
mul ( 3 cycles) line 1 ---------------_
add/sub/cmp ( 2 cycles) line 2 --->----|\_ \ _
shift/rot ( 2 cycles) line 3 --|\____|/ \ \__| "-_
popcnt ( 2 cycles) line 4 >-|/ \_|\____| "-.
leading bits ( 1 cycle ) line 5 --------------|/ | MUX |____ to outp. reg.
inc/dec/abs ( 1 cycle ) line 6 --------------------| |
sign extend ( 1 cycle ) line 7 --------|\__________| _-"
bitwise ( 1 cycle ) line 8 --|\____|/ |_-"
passthrough ( 1 cycle ) line 9 --|/
memory or imm read line X ----=> muxed into line 4
Unit 6 (Type D): << Should not be very tight; if it is, then it should be trimmed
div pipelined (38 cycles) --|\__
isqrt (26 cycles) --|/ \_|\__...----=> muxed into line 2
mul long ( 6 cycles) --------|/
mul ( 3 cycles) line 1 ---------------_
add/sub/cmp ( 2 cycles) line 2 --->----|\_ \ _
shift/rot ( 2 cycles) line 3 --|\____|/ \ \__| "-_
popcnt ( 2 cycles) line 4 >-|/ \_|\____| "-.
leading bits ( 1 cycle ) line 5 --------------|/ | MUX |____ to outp. reg.
inc/dec/abs ( 1 cycle ) line 6 --------------------| |
sign extend ( 1 cycle ) line 7 --------|\__________| _-"
bitwise ( 1 cycle ) line 8 --|\____|/ |_-"
passthrough ( 1 cycle ) line 9 --|/
memory or imm read line X ----=> muxed into line 4
Unit 7 (Type L2RF): << Should not be very tight;
L2 registers ( 1 cycle )
inc/dec/abs ( 1 cycle )
Unit D result ( 1 cycle )
sign extend ( 1 cycle )
passthrough ( 1 cycle )
memory or imm read (to output register)
